Cleanroom

Both thin and thick functional layers must reliably fulfill their (di-)electric, mechanical, optical, or piezoelectric functions while also being compatible with the entire manufacturing process. Key factors here include the material system, the required layer thickness, the available temperature budget, conformality on a wide variety of structured surfaces, and the properties of the substrate. Subsequent manufacturing steps, such as lithography, etching, bonding, or packaging, must also be taken into account early on. The goal is to reproducibly produce insulating, conductive, semiconducting, and functional layers for use in MEMS and power electronic components and to integrate their deposition into coordinated process chains. An inappropriate choice of process or uncoordinated process parameters can lead to loss of function, insufficient layer quality, or limited patterning capability of the device.

• CVD: LPCVD and PECVD for silicon compounds and dielectric or semiconducting layers.
• PVD: Sputtering and electron beam evaporation for metals, metal compounds, and magnetic and piezoelectric functional layers.
• ALD: thermal, plasma-assisted, and ozone-based processes.
• EpiPoly technology for p- or n-doped silicon and thick polysilicon layers up to a thickness of 100 µm.
• Electroplating for Cu, Ni, Au, and Sn layers.
• Polymer coating with parylene.
• Project-specific needs analysis, customized selection of suitable processes and process windows, and their integration with lithography, patterning, and metrology.

Lithography precisely reproduces mask patterns in photoresist on wafer surfaces, with or without existing topography, and lays the foundation for subsequent etching, deposition, electroplating, or lift-off processes. Key challenges include controlling and maintaining the critical feature width across the entire wafer, achieving high reproducibility from wafer to wafer, and ensuring highly accurate alignment of different lithography layers. At the same time, both thin and thick resist layers must be applied uniformly and completely cover a wide variety of topographies. Substrates made of specialty materials such as glass, GaN, or SiC also place special demands on coating, alignment, and exposure. The goal is consistently stable, reproducible, and integrable pattern transfer. Deviations in CD, overlay, or resist thickness can distort geometries, shift functional layers, and thereby impair overall functionality, process yield, and transferability.

• Optical i-line stepper lithography with 1:2 and 1:5 projection.
• Contact and proximity exposure with a mask aligner, including front- and back-side alignment.
• Spin and spray coating; positive and negative resists; thin and thick resists.
• Multilayer lithography, lift-off, high-resolution, and thick resist processes.
• Additional services: process and recipe development, resist selection, dose/focus optimization, process integration, CD/overlay characterization, profilometry, prototyping, and technology transfer.

In layer and wafer patterning, different materials must be selectively removed without adversely affecting the mask, adjacent layers, or the substrate. Material stacks consisting of dielectrics, metals, functional layers, (poly)silicon, and thin or thick dielectrics each require tailored dry or wet etching processes. Depending on the component, isotropic or anisotropic etch profiles, high aspect ratios, and very small or very large apertures in a wide variety of materials are required. At the same time, cleaning, resist removal, and thermal post-treatment must be compatible with the temperature budget of the process chain. The goal is to achieve reproducible geometry with appropriate selectivity and good surface quality relative to the underlying interface. Inappropriate processes can cause profile deviations, material damage, residues, or loss of functionality.

• Dry etching: Etching of dielectric layers, metals, and hard materials, as well as deep etching of silicon (DRIE); also processes for functional layers, glass, and thick oxide layers.
• Wet etching for a broad range of materials, as well as spin-etch processes for selected metals.
• Cleaning: RCA cleaning with SC-1 and SC-2, Piranha cleaning, diluted HF, and DSP and HVS processes.
• Chemical resist stripping and lift-off.
• Thermal processes: Annealing and Rapid Thermal Processing (RTP).
• Project-specific needs analysis, selection of suitable patterning methods and process windows, and their integration with lithography and metrology. Upstream and downstream coating and patterning steps are taken into account holistically.

Wafer bonding and (vacuum) wafer-level packaging (vWLP) enable the bonding of flat, patterned, or specially shaped wafers and protect sensitive structures through functional or hermetic encapsulation. The quality of the bond depends on material pairing, surface condition, bond frame, temperature budget, alignment, and the desired internal atmosphere. At the same time, upstream and downstream steps such as cleaning, metallization, lithography, etching, wafer thinning, and characterization must be taken into account. The goal is a mechanically stable, sufficiently tight, and electrically functional bond that withstands subsequent operational and reliability requirements. Unsuitable surfaces or process conditions can lead to incomplete bond areas, leaks, warping, contact problems, or premature failure.

• Anodic, eutectic, glass frit, and direct/fusion wafer bonding.
• Temporary, resist-based bonding using carrier concepts.
• Wafer-level packaging with application-specific process combinations.
• Glass and silicon cap connections with a defined internal atmosphere and application-specific capping.

Mechanical wafer processing and chemical-mechanical polishing (CMP) adjust a wafer’s thickness, surface, and geometry to meet the requirements of subsequent processing or characterization steps. During grinding, material must be removed efficiently without causing excessive damage, warping, or breakage. CMP planarization at ISIT enables highly controlled material removal and the planarization of qualified material systems. This process takes into account the different materials as well as contamination classes. During separation via bladedicing, the cutting path, alignment, and mechanical stress must be tailored to the device and substrate. The goals are defined final thicknesses, flat and suitable surfaces, and precisely separated components. Inappropriate processing parameters can cause chipping, cracks, surface damage, dimensional deviations, or reduced component yield.

• Grinding for thickness reduction of silicon and glass.
• Semi-automatic and fully automatic blade dicing.
• IR alignment, ultrasonic-assisted dicing, and circular cutting.
• CMP in a CMOS-compatible process line, as well as material tracks for Si, SiO, SiC, and GaN.

Metrology, characterization, and reliability testing provide the data foundation for process control and component evaluation. Depending on the specific application, it may be necessary to determine layer thickness, geometry, surface structure, material properties, electrical characteristics, or behavior under thermal, mechanical, electrical, and environmental stresses. The challenge lies in combining appropriate methods for wafers, chips, and packages and assigning measurement results to the respective process steps. The goal is to achieve a traceable and robust evaluation throughout the entire development chain so that deviations can be detected early and process windows can be validated. Inappropriate or incomplete characterization can leave relevant failure mechanisms undetected and limit the comparability and validity of development and reliability results.

• Material and Structural Metrology in the Cleanroom: Reflectometry, ResMap, optical inspection, wafer geometry, white-light interferometry, profilometry, CD-SEM, and particle scanning.
• Analytical Laboratory: AFM, XRD, XRR, SEM, X-ray analysis, XRF, laser microscopy, and 2D/3D X-ray tomography, double-beam laser interferometer (DBLI).
• Electrical characterization using semi-automatic and fully automatic wafer or chip testers.
• Reliability and environmental testing, as well as combined electrical-thermal-mechanical tests.