Wafer-Level Packaging

Manufacturing of silicon or glass cap wafers, a variety of wafer bonding processes, and the patented “Neon ultra-fine leak test” form the basis of wafer-level packaging.

more info

Glass Micromachining

The high-temperature viscous glass flow process enables manufacturing of glass packages with spherical or inclined optical windows as well as mirrors and lenses.

more info

Individual Processes

Besides a complete process chain Fraunhofer ISIT offers its customers the opportunity to make use of only individual processes.

more info

Wafer-Level Packaging and Processes

Fraunhofer ISIT has a modern 200 mm clean room line for development and production of microsystems out of silicon and glass. Due to the longtime experience in development and manufacture of MEMS and MOEMS components ISIT has a broad portfolio of mature individual processes as well as diverse process platforms. Existing processes can be adapted to the customer needs to realize custom specific solutions, which can be transferred to pilot production on a short time scale.

The hermetic encapsulation of the components within the manufacture of micro-mechanical and micro-optical systems at wafer level is one of the major challenges. In line with the general miniaturization the traditional enclosures made of metal or ceramics are being replaced by caps made of silicon and glass, which are already hermetically connected to the component at wafer level. As one of the leading development service providers in the field of wafer-level packaging Fraunhofer ISIT provides a large process portfolio for cap wafer production based on silicon and glass wafers and their connection to each other.

The manufacture of lenses and glass caps based on the patented high temperature viscous glass flow process is a specialty of Fraunhofer ISIT. Depending on the application spherical or planar surfaces with high optical quality can be manufactured, whereby the slope of the planar surfaces can be freely selected.

Wafer-Level Packaging

Glass Micromachining

Processes on Wafer-Level