Bumping and Balling

Application of solder by galvanic processing, paste printing, and placement of discrete solder balls as well as stud bumping.

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Under-Bump Metallisation

Maskfree, electroless deposition of Ni/(Pd)/Au bumps on Aluminum or Copper to achieve solderability.

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Electrical Through-Connections

Hermetically sealed electrical through-connections (vias) in glass or silicon wafers.

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Sealing Frames

Hermetic sealing frames with lateral feedthroughs enable a unique combination of CMOS wafers and MEMS.

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Chip-Size Packaging

The massive increase of microstructured components in mobile electronic devices necessitates extremely miniaturised components with thicknesses below 1 mm. The Fraunhofer ISIT is specialized on the advanced hybrid integration of micro components like inertial sensors with their electronic driver circuits. This assembly concept can, depending on chip geometry and complexity, also be executed on wafer level (WL-CSP), which allows particularly thin assemblies.
The institute has developed a modular toolbox of key technologies that allow a rapid customer specific component development, like the following:

  • symmetrical wafer thinning of MEMS components
  • special dicing techniques, e.g. to expose wirebond pads
  • electrical feedthrough in glass and silicon wafers (TSV: Through-Silicon Via)
  • chip-stacking technique with adhesive transfer foils
  • spacer technology for chip mounting
  • 3D wire bonding and
  • bumping and balling with solder preforms, paste or gold stud-bumps